`timescale 100ns/100ns
module frq_tb (
    
);

reg clk,rstn;
wire clk_1k;
frq frq(
     .clk(clk)
    ,.clk_1k(clk_1k)
    ,.rstn(rstn)
);

initial begin
   clk = 1'b0;
   rstn = 1'b0;
 end

always  begin
    #20 rstn = 1'b1;
    #20 rstn = 1'b0;
    #20 rstn = 1'b1;
    #5000000000;
end

always  begin
  #5 clk = ~clk;
end
endmodule //frq_tb